In a common BiCMOS architecture in which the emitter is manufactured in a self-aligned way relative to the collector and the base, the emitter silicon is patterned by means of a damascene process. However, this process flow inevitably results in the upper edge of the emitter silicon to be located above the upper edge of the CMOS gate. Due to the longer feed line length, this result in an increase in the emitter resistance, which has a negative impact on the switching frequency of the bipolar device.
Up to now, the emitter is patterned by a poly-CMP process (CMP=chemical mechanical polishing) with a stop on the GC topography (GC=Gate Conductor). This results in pattern breaking at the wafer edge and in a strong dependence of the emitter height on the specific layout (occupancy density, surroundings) of more than ±30 nm among various layouts.
Therefore, it would be desirable to have a concept for manufacturing a BiMOS device that allows adjusting an height of an emitter of a bipolar junction transistor of the BiMOS device (substantially) independent on a height of a gate of a MOS device of the BiMOS device.